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1. The Atari TT hardware

  The MC68030 CPU
  The MC68030 in the Atari TT is a real 32-bit processor which is
  mainly 68000 compatible. The biggest advantage is the on-chip Data
  and Instruction caches of 256 byte length each.
  The caches can be manipulated by the Cache-Control-Register (CCAR)
  which is a part of the MC68030 itself (hiword is always zero!):

   15 .......................................................... 0
    0   0   WA  DBE CD  CED FD  ED  0   0   IBE CI  CEI FI  EI

   WA  = Write allocate                IBE = Instruction Burst enable
   DBE = Data Burst Enable             CI  = Clear Instruction Cache
   CD  = Clear Data Cache              CEI = Clear entry in Inst.cache
   CED = Clear Entry in Data cache
   FD  = Freeze Data cache             FI  = Freeze Instruction cache
   ED  = Enable Data cache             EI  = Enable Instruction cache

   To completely disable one of the caches, you have to set the
   "Enable cache" bit to zero. "Freezing" the cache makes it work
   almost as a ROM - All Reads will be applied to the cache, but its
   contents will not be overwritten. To clear one whole cache, use
   the CD- or CI-bits. To clear a certain cache-entry, you will have
   to use the CEI- or CED-bits in conjunction with the
   Cache-Address-Register (CAAR) - also on chip - which contains the
   address of the cache entry. However, only bits 7 to 2 are being
   used currently in the CAAR, so only these bits have to be set.
   Burst mode enables extremely quick update of the cache which allows
   128-bit to be read more or less at once.

   The MC68030 PMMU
   The "paged memory management unit" of the MC68030 inside the Atari
   TT is capable of converting "virtual" adresses used by programs
   into "physical" adresses used by the hardware. This easily allows
   memory protection, mostly used by multitasking systems like Unix
   and MiNT or virtual memory that is actually on a harddisk.
   This device is usually not being used by games- or demo-programmers
   so it will not be discussed here in any way.

   The MC68882 FPU
   The MC68030 was designed to cooperate with an MC68882 without any
   additional hardware- or software modification. The duo MC68030 and
   MC68882 work almost like they were on one chip, which makes it
   extremely easy for the programmer to handle the duo.
   The FPU features 8 floating point registers (FP0 to FP7) of 80 bits
   length each, it has its own Control Register (FPCR) and Status
   Register (FPSR) as well as its own Instruction adress register
   The MC68882 communitcates with the MC68030 over the so-called LineF
   emulation (all instructions of the MC68030 that adress the FPU have
   "F" as the first hexadecimal digit).
   The FPU itself bears 64 instructions and 5 new instruction-width
   indices (Integer, Single Real, Double Real, Extended Real and
   Packed Decimal Real Data Format).

   The details on FPU-programming will not be discussed in detail in
   this documentation. Please refer to an MC68882 Programmer's Manual
   by Motorola.

  Compatibilities and incompatibilities
  => In comparison to the Atari ST and Atari STE:
     These series only bear an MC68000 which has a few "disadvantages"
     in comparison to the MC68030 of the Atari TT.
     First, the external data bus is only 16-bits wide which makes
     reading and writing of a longword slower than of a word. In the
     Atari TT, reading or writing 16-bits at once makes absolutely no
     difference to reading or writing 32-bits.
     The 68000 does not have adress line 0, which makes it impossible
     for the MC68000 to read 16- or 32-bits from odd addresses
     (reading bytes is possible since the 68000 reads a 16-bit-word in
     fact and only leads through the required 8 bits) - The attempt to
     do this will lead to an error on the ST. The TT can read words
     and longwords from any given address.
     The 68000 has no cache. Attempting to set the caches will either
     crash the machine or have no affect at all (untested).
     The condition code register of the MC68030 and 68000 are
     identical. The other bits of the Status Register (8 to 31) are
     NOT identical. Handle with care.
     The 680x0-instructions MOVE from/to SR are allowed in USER-mode
     on the 68000, on the MC68030, they are NOT. The TOS of the TT has
     a patch for that by executing an exception, but in case the
     desired program shall not require or refer to TOS routines, this
     will have to be acknowledged.
     Furthermore, the MC68030 has additional ways of adressing and can
     multiply/divide longword operands. These instructions will
     generate an error on the MC68000.

  => In comparison to the Atari Falcon030:
     Both computers have an MC68030 with its caches and both have a
     PMMU. If equipped with an MC68882, the Falcon can also operate
     FPU-instructions just like the TT, if the FPU misses, they will
     generate an error.
     The bus-system of the Falcon does not allow burst-mode in
     memory-access. Setting this bit in the CCAR will not change

  => What to look out for when writing ST-programs:
     The MC68030 is a 32-bit processor and has - basically - a 32 bit
     adress bus. The MC68030 will not work well if being fed 24-bit
     adresses only, which works on the ST.
     Also make sure to access the Condition Code Register instead of
     the whole Status Register if not in Supervisor mode. These
     instructions on the MC68030 are only allowed as Supervisor.
     Also, clockcycle-based effects will never work correctly on ST
     and TT. First, instruction timing on the 68030 is not only
     different to that on 68000, but also more flexible due to cache
     and RAM-usage. Besides that, the clockspeed of the TT is not
     controlable and always runs at 32 MHz - In contrast to the Falcon
     which is switchable to 8 MHz.

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